The present invention relates to a semiconductor design technology, and more particularly to a clock generator using an injection locking scheme and a clock synchronization circuit using the same.
Generally, a semiconductor memory device including a double data rate synchronous dynamic random access memory (DDR SDRAM) receives an external clock signal to generate an internal clock signal, and uses the internal clock signal as a reference for adjusting various operation timings in the semiconductor memory device. Therefore, a clock synchronization circuit must be included in the semiconductor memory device in order to generate the internal clock signal synchronized with the external clock signal. Representative examples of such a clock synchronization circuit include a phase locked loop (PLL) and a delay locked loop (DLL).
The PLL and the DLL have similar configurations. However, the PLL employs a voltage controlled oscillator (VCO) to generate the internal clock signal, whereas the DLL uses a voltage controlled delay line (VCDL). The VCO and the VCDL may be divided into an analog method and a digital method in accordance with a control scheme.
In the field of a semiconductor memory device, various researches have been conducted to increase operating speed, reduce power consumption and remove jitters mixed in an external clock signal.
A part of such researches is adopting an injection locking scheme. The injection locking scheme is a method that an oscillation signal output from a master oscillator is injected into a slave oscillator in order to synchronize an oscillation signal output from the slave oscillator with the oscillation signal output from the master oscillator. A circuit designed in this manner can reduce power consumption and improve operation performance with respect to the jitters. The injection locking scheme will be described in more detail with reference to FIG. 1.
FIG. 1 is a block diagram of a clock generator using a general injection locking scheme.
Referring to FIG. 1, the clock generator using the general injection locking scheme includes a main oscillator 110 serving as a master oscillator, and an injection locking oscillator 130 serving as a slave oscillator.
The main oscillator 110 generates a positive main oscillation signal M_OSC having a frequency corresponding to the voltage level of an input control voltage V_CTR and a negative main oscillation signal M_OSCB having a phase opposite to that of the positive main oscillation signal M_OSC. The main oscillator 110 may have a minimum frequency and a maximum frequency according to the voltage level of the control voltage V_CTR. Hereinafter, such a frequency range will be referred to as the operating frequency range of the main oscillator 110.
The injection locking oscillator 130 is implemented as a ring oscillator including a first delay cell 132 and a second delay cell 134. The first delay cell 132 receives a positive final oscillation signal FIN_OSC and a negative final oscillation signal FIN_OSCB, which are the output signals of the second delay cell 134, through its input terminals, and outputs signals synchronized with the positive main oscillation signal M_OSC. The second delay cell 134 receives the output signals of the first delay cell 132 through its input terminals, and outputs the positive final oscillation signal FIN_OSC and the negative final oscillation signal FIN_OSCB which are synchronized with the negative main oscillation signal M_OSCB.
FIG. 2 is a circuit diagram illustrating the injection locking oscillator 130 of FIG. 1. In FIG. 2, only the first delay cell 132 is illustrated for the convenience of description. Furthermore, the first delay cell 132 and the second delay cell 134 have similar configurations. The difference between the first delay cell 132 and the second delay cell 134 is that the first delay cell 132 includes an NMOS transistor NM having a gate receiving the positive main oscillation signal M_OSC, whereas the second delay cell 134 includes an NMOS transistor (not shown) having a gate receiving the negative main oscillation signal M_OSCB.
Referring to FIG. 2, the first delay cell 132 includes an input/output unit 210, a loading unit 230, and a current control unit 250.
The input/output unit 210 receives the negative final oscillation signal FIN_OSCB through a first input terminal IN, and receives the positive final oscillation signal FIN_OSC through a second input terminal INB. Furthermore, the input/output unit 210 outputs differential output signals through first and second output terminals OUT and OUTB in response in synchronization with the positive main oscillation signal M_OSC.
The loading unit 230 has a loading value corresponding to a first resistor R1 and a second resistor R2, wherein the loading value is a factor that determines the RC delay of a circuit.
The current control unit 250 includes the NMOS transistor NM having a drain connected to a common node N, a source connected to a ground voltage terminal VSS, and a gate receiving the positive main oscillation signal M_OSC. The current control unit 250 controls current flowing through a current path between the common node N and the ground voltage terminal VSS in response to the positive main oscillation signal M_OSC.
On the main oscillation signal and the final oscillation signal, the positive and negative final oscillation signals FIN_OSC and FIN_OSCB have a frequency obtained by dividing the frequency of the positive main oscillation signal M_OSC by 2. For example, if the positive main oscillation signal M_OSC has a frequency of 4 GHz, each of the positive final oscillation signal FIN_OSC and the negative final oscillation signal FIN_OSCB has a frequency of 2 GHz. At this point, the phenomenon that the output signals of the injection locking oscillator 130, i.e., the final oscillation signals, are synchronized with the main oscillation signals is referred to as an injection locking.
Since the injection locking is the general phenomenon of circuits adopting the injection locking scheme, its detailed description will be omitted.
Referring again to FIG. 1, the main oscillator 110 generates the positive main oscillation signal M_OSC and the negative main oscillation signal M_OSCB and injects the generated signals into the injection locking oscillator 130. In this case, the injection locking oscillator 130 outputs the positive/negative final oscillation signals FIN_OSC and FIN_OSCB having a frequency obtained by dividing the frequencies of the positive/negative main oscillation signals M_OSC and M_OSCB by 2 in accordance with the injection locking. Herein, the injection locking oscillator 130 is a divider that divides a frequency of an input signal by 2.
Meanwhile, the frequencies of the positive/negative main oscillation signals M_OSC and M_OSCB and the free running frequency of the injection locking oscillator 130 must satisfy a desired condition for the occurrence of the injection locking. The relationship between the frequencies of the positive/negative main oscillation signals M_OSC and M_OSCB and the free running frequency of the injection locking oscillator 130 will be described below.
In order for the occurrence of the injection locking, i.e., in order for exactly dividing the frequencies of the positive/negative main oscillation signals M_OSC and M_OSCB by 2, the free running frequency of the injection locking oscillator 130 must be placed at approximately half the frequencies of the positive/negative main oscillation signals M_OSC and M_OSCB. Otherwise, the injection locking does not occur in the injection locking oscillator 130 so that the frequencies of the positive/negative main oscillation signals M_OSC and M_OSCB are not correctly divided. This phenomenon often occurs in circuits to which the injection locking scheme using the circuit configuration of FIG. 2 is applied.
Herein, the frequency range of the positive/negative main oscillation signals M_OSC and M_OSCB in which the injection locking can occur is referred to as an injection locking range, and the injection locking range is about 1/10 times the free running frequency of the injection locking oscillator 130.
Assuming that the frequencies of the positive/negative main oscillation signals M_OSC and M_OSCB intended to be finally output from the main oscillator 110 are 4 GHz and then the free running frequency of the injection locking oscillator 130 is fixedly to 2 GHz, the injection locking range is about 1/10 times the frequency of 2 GHz. Therefore, the injection locking can be achieved when the frequencies of the positive/negative main oscillation signals M_OSC and M_OSCB are placed within the frequency range from 3.9 GHz to 4.1 GHz. That is, the injection locking can occur in the injection locking oscillator 130 only when a free running frequency of the main oscillator 110 is placed within the frequency range from 3.9 GHz to 4.1 GHz. Furthermore, when the frequencies of the positive/negative main oscillation signals M_OSC and M_OSCB which are finally output from the main oscillator 110 is 4 GHz, the injection locking oscillator 130 exactly divide the frequencies of the positive/negative main oscillation signals M_OSC and M_OSCB by 2 to output the positive/negative final oscillation signals FIN_OSC and FIN_OSCB having the frequency of 2 GHz.
In other words, the range of the free running frequency of the main oscillator 110 is limited in accordance with the fixed free running frequency of the injection locking oscillator 130. This means that the operating frequency range of the main oscillator 110 capable of dividing the frequency by 2 is limited within the injection locking range.
Meanwhile, the DLL and the PLL, which are a clock synchronization circuit, include a divider. If the injection locking scheme is applied to the divider used in the PLL and the DLL, the PLL and the DLL can reduce power consumption and improve operation performance with respect to jitters. However, the divider using the injection locking scheme is difficult to design in the PLL and the DLL operating in a broad operating frequency range because of the following reasons.
If operating frequency ranges of signals which the VCO of the PLL or the VCDL of the DLL intends to output are in the range from 1 GHz to 5 GHz (the VDCL delays an input signal, but the frequency range of an output signal may be varied in accordance with the frequency of the input signal), the divider using the injection locking scheme must also divide all the frequencies of 1 GHz to 5 GHz. However, since the free running frequency of the divider using the injection locking scheme is fixed, most of the frequencies of 1 GHz to 5 GHz get out of the injection locking range. Accordingly, it is almost impossible to apply the injection locking scheme to the divider included in the PLL and the DLL.
Consequently, the injection locking scheme must limit the operating frequency range of the oscillation signal injected in the injection locking oscillator 130 to the injection locking range. Although the injection locking scheme can reduce power consumption and improve operation performance with respect to the jitter, it is almost impossible to apply the injection locking scheme to the clock synchronization circuit.